Circuito Integrado Sn74hct138n 74hct138 Dip-16

Descripción

SNx4HCT138 3-Line to 8-Line Decoders/Demultiplexers.

1 Features
- Operating voltage range of 4.5 V to 5.5 V
- Outputs can drive up to 10 LSTTL loads
- Low power consumption, 80-µA max ICC
- Typical tpd = 17 ns • ±4-mA output drive at 5 V
- Low input current of 1 µA max
- Inputs are TTL-Voltage compatible
- Designed specifically for high-speed memory decoders and data transmission systems
- Incorporate three enable inputs to simplify cascading and/or data reception.

2 Description
The ’HCT138 devices are designed for highperformance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

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